A common goal in the fabrication of integrated circuitry is to minimize the surface area of the integrated circuit required for various structures. This goal is of particular importance in the fabrication of digital memory circuitry. Because each memory cell in a memory circuit is repeated, small savings of surface area in the memory cells leads to large savings in the overall surface area of the integrated circuit. To this end, vertical DRAM cells have been developed such as the invention of Chatterjee et al., U.S. patent application Ser. No. 679,663, filed on Dec. 7, 1984, which is assigned to the Assignee of the present application and is hereby incorporated by reference.
A one transistor DRAM cell usually consists of a control transistor having a gate and source controlled by external word and bit lines and a drain connected to a capacitor which has its opposite plate grounded. Data is written into the memory cell by storing charge on the capacitor. Because charge will eventually leak off the capacitor, the cell must be periodically refreshed. The amount of time between refreshed cycles is increased by increasing the capacitance of the capacitor. Thus increased capacitance is desirable with this type of DRAM cell. In addition, stray fields, alpha particles and charges in the substrate may effect the charge stored on the capacitor if the ungrounded plate of the capacitor is not insulated from the substrate. Thus it is desirable to provide a storage capacitor having an ungrounded plate which is insulated from the substrate.